In recent years, the rapid development of high-speed railway in our country, followed by a rail safety problem has become the most important issue, as the core of the train operation control equipment, the development of the safety critical computer should be considered, firstly. At present, the mainstream safety critical computers all adopt the method of isomorphism, which can eliminate the multiple non-common fault of the same error structure, but can do nothing for some common fault. In this paper, a heterogeneous safety critical computer design and implementation method is proposed, which adopts the method of heterogeneous hardware and software, and analyzes its reliability and security by using fault tree model.
Published in | Science Discovery (Volume 7, Issue 4) |
DOI | 10.11648/j.sd.20190704.22 |
Page(s) | 249-256 |
Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
Copyright |
Copyright © The Author(s), 2019. Published by Science Publishing Group |
Heterogeneous, Safety Critical Computer, Reliability, Security
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APA Style
Shi He, Zhao Deliang. (2019). Design and Implementation of a Heterogeneous Safety Critical Computer. Science Discovery, 7(4), 249-256. https://doi.org/10.11648/j.sd.20190704.22
ACS Style
Shi He; Zhao Deliang. Design and Implementation of a Heterogeneous Safety Critical Computer. Sci. Discov. 2019, 7(4), 249-256. doi: 10.11648/j.sd.20190704.22
AMA Style
Shi He, Zhao Deliang. Design and Implementation of a Heterogeneous Safety Critical Computer. Sci Discov. 2019;7(4):249-256. doi: 10.11648/j.sd.20190704.22
@article{10.11648/j.sd.20190704.22, author = {Shi He and Zhao Deliang}, title = {Design and Implementation of a Heterogeneous Safety Critical Computer}, journal = {Science Discovery}, volume = {7}, number = {4}, pages = {249-256}, doi = {10.11648/j.sd.20190704.22}, url = {https://doi.org/10.11648/j.sd.20190704.22}, eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.sd.20190704.22}, abstract = {In recent years, the rapid development of high-speed railway in our country, followed by a rail safety problem has become the most important issue, as the core of the train operation control equipment, the development of the safety critical computer should be considered, firstly. At present, the mainstream safety critical computers all adopt the method of isomorphism, which can eliminate the multiple non-common fault of the same error structure, but can do nothing for some common fault. In this paper, a heterogeneous safety critical computer design and implementation method is proposed, which adopts the method of heterogeneous hardware and software, and analyzes its reliability and security by using fault tree model.}, year = {2019} }
TY - JOUR T1 - Design and Implementation of a Heterogeneous Safety Critical Computer AU - Shi He AU - Zhao Deliang Y1 - 2019/08/27 PY - 2019 N1 - https://doi.org/10.11648/j.sd.20190704.22 DO - 10.11648/j.sd.20190704.22 T2 - Science Discovery JF - Science Discovery JO - Science Discovery SP - 249 EP - 256 PB - Science Publishing Group SN - 2331-0650 UR - https://doi.org/10.11648/j.sd.20190704.22 AB - In recent years, the rapid development of high-speed railway in our country, followed by a rail safety problem has become the most important issue, as the core of the train operation control equipment, the development of the safety critical computer should be considered, firstly. At present, the mainstream safety critical computers all adopt the method of isomorphism, which can eliminate the multiple non-common fault of the same error structure, but can do nothing for some common fault. In this paper, a heterogeneous safety critical computer design and implementation method is proposed, which adopts the method of heterogeneous hardware and software, and analyzes its reliability and security by using fault tree model. VL - 7 IS - 4 ER -